1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a multi-chip package device to which a unified memory technology is applied. This application claims priority from Korean Patent Application No. 10-2005-0023012 filed on 21 Mar. 2005, the entirety of which is hereby incorporated herein for all purposes as if fully set forth herein.
2. Description of the Related Art
Recently, a multi-chip packaging technology that integrates two or more individual memory chips into a signal package device has been developed. In accordance with the multi-chip packaging technology, processors and memory chips, logic chips and memory chips, or memory chips alone are mounted in a single package. A multi-chip package device, in which two or more individual memory chips are mounted in a single package, is advantageous in that the manufacturing cost thereof can be reduced and the miniaturization thereof can be achieved.
A multi-chip package device in which two memory chips are mounted in a single package or housing is disclosed in U.S. Pat. No. 6,366,487 entitled “Plurality of Integrated Circuit Chips,” which is incorporated herein by reference. In accordance with this patent, first and second memory chips included in a single package are configured to share external pins (for external addresses, external control signals and data). The first and second memory chips included in the single package are distinguished from each other by option voltages applied to an option pad. The first and second memory chips are each implemented in the form of unified memory that stores code and data in a single piece of memory. Furthermore, necessary code and data are temporarily stored in buffer memory and the buffer memory is accessed when necessary.
Meanwhile, in the multi-chip package device, a priority processing command can be issued. When such a priority processing command is issued, access to boot code, prior to accessing general data or code, is required to perform the priority processing command. Accordingly, the multi-chip package device also requires efficient storage of the boot code capable of executing the priority processing command, and a technology for efficiently accessing the boot code.
Accordingly, it would be desirable to provide a multi-chip package device having two or more memory chips to which a unified memory technology is applied, and a method of driving the multi-chip package device, which can not only efficiently store boot code capable of performing a priority processing command, but also efficiently access the boot code.